New Release v0.17.4
Optimizations for faster and smaller designs
This release delivers significant performance improvements through simplifying logic and the way we handle constants. The result is faster and smaller arithmetic and logic operations, improved latch removal, and the ability to have multiple operators per clock cycle.
Our current tooling version is
reco v0.5.2. You can run
reco version to check your current installation.
If you need to upgrade, and have v0.5.0 or above, you can simply run
reco update to be guided through the process.
To update from a version before v0.5.0 you can follow our instructions here: http://docs.reconfigure.io/setup.html#install-update-the-command-line-tool
New cost system for latch removal based upon FPGA timing delay
Through deeper analysis of the timing delays introduced by various FPGA logic components, our engineering team has been able to work out ways to combine logic components into a single pipeline stage, leading to overall performance improvements for your applications.
This, combined with operators now being able to run in partial cycles, lets us perform simple arithmetic functions like
(a + 1) < b in a single clock cycle.
The optimizations in this release result in faster and smaller logical and arithmetic operations. An example of where this has made a big impact on our designs is with our MD5 hash example which is now 97% smaller and 20% faster. This is an extreme example due to the heavy use of simple logic and arithmetic operations but we estimate most designs will see a 20% size reduction and 20% speed increase.
For a full rundown of this release, see our release notes.