New Release v0.18.1
New features for our new beta compiler
BlockRam generation and register-based scheduling have now been enabled in our new beta compiler.
Activating the new compiler in your projects
For the next few weeks we will be supporting both old and new compiler models to avoid any compatibility issues for our users, and to ensure we sort out any bugs before adopting it as our core tech. So, for now, to use the new compiler version, just add this line to your project’s
Without this, the old compiler model will still be used when running sims and builds.
Note that the new compiler is in beta so if you hit any bugs or issues please let us know on the forum
Our current tooling version is
reco v0.6.0. To check your version and update if required, please run:
When using the new compiler, Rio, blockRAMs are now generated for designs that use arrays larger than 512 bits. Xilinx FPGAs contain multiple blockRAM components as an alternative to storing data with LUTs.
Register-based scheduling has been incorporated into the new compiler with this release, which allows for more parallelism by allowing independent, non-combinational components of a design to be scheduled in parallel.
For a full rundown of all our releases, see our release notes.
Over the coming weeks the compiler team will be refining the new LLVM-based model before moving our service over to use it as standard. Following that there are more optimisations and tooling improvements to come.