🎉 Reconfigure v0.16.4 is released 🎉


New Release v0.16.4
Compiler optimizations and a tooling upgrade

Our engineering team have been busy analyzing our code generation to locate optimizations for maximizing concurrency and speed, while reducing latency and FPGA area usage.


There’s a new version of our command line tool, reco v0.4.4. We’ve improved the in-built help and fixed bugs. This release is recommended for all users.

To upgrade, follow our instructions here.

Reducing the cost of function calls

Due to the complexity of code generation in our complier, the control flow used for function calls was unnecessarily complex. This update simplifies this control flow, which not only speeds things up, but also allows other optimizations to be performed across function calls, potentially improving performance even further. At this stage most users should notice a slight reduction in FPGA area usage.

Optimize variable and channel concurrency operations

Through static analysis our engineers are now able to prove when concurrent operations are mutually exclusive, allowing the concurrency overhead to be reduced – this includes both FPGA area usage and latency. Further concurrency has also been unblocked through pinpointing when variable reads will always be operated on, so the operator can be pushed before writes to optimize the process.


For a full rundown of this release, see our release notes.

What’s Next?

We’re currently working on a framework for scaling up small programs into more complex systems with improved performance.


Can you elaborate “framework for scaling up small programs into more complex systems with improved performance”? What do you mean by scaling up small programs?


We have a few use cases where it’s easy to describe how to solve the problem for a single instance serially, but it’s not easy to necessarily scale that up to use the full FPGA to solve it in parallel. We’re working on separate tooling & frameworks to automate this for some of these cases.


I see, thanks, interesting!