👋 Introductions! 👋


Reconfigure.io is a service built around its users and our community is a vital part of how we develop.

We would really like to hear about what has brought you here and what you hope to get out of using Reconfigure.io, so please introduce yourself by replying to this post…



Heya, I’m Toby - a Go dev from Bristol with a slight enthusiasm for hardware! Reason I came to Reconfigure is because programming FPGAs in Go sounds way more attractive than VDSL. :wink:


I’m martoni. I’m interesting by new HDL languages in FPGA. I already design with Chisel (Scala) and MyHDL (python). Then I’m curious with this new Go HDL language.


Hi everyone,

thanks for the invitation. At my company we’re working on a similar product but for .NET developers, called Hastlayer.

While the two products are similar, I think both have their unique advantages and can ultimately make the FPGA scene bigger, so I’d like to see some cross-pollination.

Zoltán - architect of Hastlayer


Hi all,

I am Stefan, a Free and Open Source Silicon enthusiast and FPGA developer. Looking forward to working with a very innovative tool!



Hei, I am Antti. I have been doing some FPGA-development with Verilog. Using Go to same things sounds very interesting!



I’m Marcus. I use LabVIEW FPGA to graphically program FPGAs for a variety of applications such as machine learning for predictive maintenance, low latency simulation, controlling fusion reactors and many more. I just wanted to check out using GO in a similar fashion.


:wave: Welcome everyone! :wave:


Hello everyone!
Thanks for the invitation.
I am Foutse, working on implementing machine learning algorithms on FPGA with Chisel(Scala) HDL.
I will be glad to learn and expirience Go and make the difference with Chisel.


Hi everyone!

I am Maartje, DevOps at Innovate Group where I spend a huge part of my time in Go. I’ve been trying to learn VHDL but haven’t gotten to it, so being able to use a language I love to speed up high perfomance code would be amazing!



I’m Mark - based in Italy. I’ve a long history with FPGAs, especially with RTLs such as VHDL and SystemVerilog.

I’m interested in any kind of high-level language for FPGA and to see how Go stacks up against C/C++ based solutions.


Hi all :slight_smile:

I am Wen. I am an embedded software developer in an IoT startup. I am also a go developer. Our company focuses on identifies problems and using iot techs to solve it. So we do a lot of prototyping in techs. For me its super cool to use go instead traditional hardware language on FPGA.


Hi everyone,

I have a piece of hardware that requires outdated proprietary software/closed firmware to operate. When it got bricked once I noticed I had to upload VHDL to it to get it to work again. I don’t know fpga programming but I do know Go so I’m looking to see if I can get it to operate all with open code.



I’m Alex, a FPGA developer in Kansas, USA. My company is looking to shorten development time for internal and client-based IP-cores, particularly emphasizing in Machine Learning, Flight-Control, Computer Vision, and Object Tracking.



I am the FPGA design lead for RFNoC (ettus.com/sdr-software/detail/rf-network-on-chip). I am always interested in new HDLs to make it easier for our users to write their custom accelerators. I’ve tried out VivadoHLS, Chisel, and MyHDL. I am looking forward to giving this a try.


Hi all!

I am a student working on research that utilizes neural network architectures that can be efficiently implemented on FPGAs for embedded applications. Looking forward to using Go instead of churning out Verilog :slight_smile:.


Hello! I’m Alexey - based in Russia. Thanks for invitation!
I know about the project thanks to hackaday.com . I have a little experience with Go, but I prefer Erlang / Elixir (this is my work). I like comparing the performance and approaches to the solution between Go and Erlang. My hobbies - HAM radio (SDR FPGA); analog and digital audio design, analog & digital music/sound synthesis (I am developing my FPGA based open project (on Verilog)).
I would like to see the compilation of Erlang to HDL hardware. But it will be very interesting to see what happens on the basis of Go.
Good luck!


Hi everyone,
I am an undergraduate student from China. I have been working on FPGA for a year. I have learned Verilog, ALtera OpenCL etc. However, I think these tools are not very convenient. Reconfigure.io really suprised me as soon as I saw it. It could take advantage of Go programming language and I want to try it as soon as possible.

I will use Reconfigure.io to build several applications to run on FPGA to accelerate them.


Absolutely fantastic to see so many people joining the community!

I am Jono and I am a consultant who helps companies to build communities. I am working with @rob.taylor and the team at Reconfigure.io - lots of great stuff coming down the line!


Hi, everyone.
My name is Vinicius Stein, I live in Brazil, student of Electrical Engineering.
I program FPGAs by hobbie, I do several experiments using ALTERA kits, currently in an RF spectrum analyzer project and another on power quality.
I program in VHDL, python and I have a lot of experience in C for embedded. Starting now the studies in the GO Language.