👋 Introductions! 👋


#21

Brilliant to see so many folk sharing their interest here - I’m so excited to hear what sort of areas and use cases you all have in mind for Reconfigure.io!


#22

Hi, everyone.
I’m Kazuaki, living in Japan.
Thanks for the invitation!

I work in the R&D department.
My team is researching OpenStack & FPGA.
I have a little experience with Verilog HDL.
But, I’ve just started with it.
I’m very interested in Go HDL.
thanks :slight_smile:


#23

Hi everybody!
I´m Sergio. I have worked and taught High level synthesis since 2002 at University of Alicante (Spain), mainly Handel-C and now VivadoHLS. Here you can see some projects developed with HLS (https://www.youtube.com/user/segiocuen). Currently interested in acceleration of autonomous driving algorithms with PSoC based on FPGA.


#24

Hi!
Thanks for the invitation.

My name is Khanh, a “last month” Ph.D. student.
I am interested in developing FPGA/ASIC devices.


#25

Hello!

I’m Lwrless, a student in China. I’m interested in FPGA and I know Go. Programming FPGAs in Go language sounds just really great for me. Looking forward to trying this awesome tool.


#26

Hi Sergio, very impressed with your lemmings implementation in Handel-C! Would you be able to share your presentation?


#27

Hi Rob,
here you can find the presentation, unfortunately was written only in spanish and explanations are not very clear. (https://www.dropbox.com/s/cj9o0ylz3q5o61k/PresentacionLemmingsppt.pdf?dl=0)
In this opencourse (also in spanish) you can find the general schemes for designing bitmap based videogames and mixe them with an Eyetoy interface.
https://ocw.ua.es/es/ingenieria-y-arquitectura/arquitecturas-reconfigurables-2006.html
Don´t hesitate to ask for any other information.
Regards


#28

Hello everyone,

My name is Tyrone. I am a PhD candidate looking into ways to make hardware design more accessible at a high level. My official topic (at present) is automated hardware/software partitioning for high level synthesis. I have a fair amount of experience with VHDL (and am somewhat fond of the language), but I am very interested to see more high level approaches to hardware design.


#29

Thank you Sergio for sharing this! Luckily I’m not too bad at reading Spanish - I’ll find my self a quiet moment over the weekend to have a read though :slight_smile:


#30

Hello,

I am Kashif. I am interested in how can I achieve partial reconfiguration via GO HDL. I am an enthusiast. So I am here, representing myself and no organisation :slight_smile:


#31

Hey,

This is Cristian, i came across reconfigure.io because i’ve always been following FPGAs and FLOSS, well not sure how much of that there is in reconfigure.io, but the idea of use go as HDL or glue to make FPGAs more dev friendly was something that caught my attention.


#32

Hello there
My name is Alex.

We are doing some Go programming and looking for a tool to boost it enabling FPGA.
Go + FPGA looks really promising and I’d like to try it working on simple PoC

Thx


#33

Hello!

I’m Leo. I work in the snapcraft team at Ubuntu.
I am learning FPGAs with a snickerdoodle.

Being able to learn how to program the board with go sounds like a dream.


#34

Hi,

I am curious what and how to not use VHDL or RTL to program the FPGA. I work in a company previously known as Altera


#35

Hi there, my name is Theo and me and my team are working on high-performance reproducible linear algebra for sensor fusion, control, and optimization applications. All our work is on distributed and concurrent and parallel systems and we use C++ for the distributed and parallel algorithms, and Golang for the concurrent system implementations. The fact that Reconfigure.io is a Golang to hw environment attracted our attention, and we are big proponents of the CSP abstraction to build scalable concurrent systems: all our hardware designs are fundamentally CSP architectures and thus we are a very good match to the Reconfigure.io vision.

I am looking forward to interacting with the community as we are gunning for building services for AWS and we love to find collaborators in this quest.


#36

The reason we are moving up the abstraction stack is that productivity of VHDL and Verilog hw descriptions is too low for SoC work. Secondly, cloud services need to change so quickly that the parallel/concurrent hw needs to move closer to the abstractions managed by software to enable efficient transformations/realizations. The Quartus tool chain is not very good in this regard and thus we are looking for better alternatives, and Reconfigure.io is a good step towards higher productivity.


#38

Roslyn here. I am new to Golang. I am creating a prototype around Golang, FPGAs and sensors. #iot


#39

Hi All,

I am a graduate student from UCSB. Interested in FPGA based hardware acceleration for ML applications. Have already accelerated few applications using Verilog HDL and have used Vivado HLS in the past. Looking forward to the Go HDL! I’m also looking out for internship/full time in hardware acceleration post graduation.

Regards,
GP