I am testing a bit reconfigure.io and trying to understand the philosophy of the high level synthesis in this tool. Sorry if I ask the question in the wrong place or if it has already been discussed.
I have been testing Tutorial 3 and I see that you recommend unrolling loops manually in the code. The whole complexity of other HLS tools (like Vivado HLS for example) is due to their automatic loop unrolling and pipelining.
Using reconfigure.io, is it possible to write the example in Tutorial 3 in an optimized way, while keeping it generic (so that the number of elements can be a parameter instead of fixed to 8)?
It seems possible to do so by generating one channel for each input value, and generating the right number of go routines to sum these numbers.
Also, do we have control on how data is stored in the FPGA? For example, in Tutorial 3, if “array” is stored in registers, the sum can be fully parallel, but if it is in BlockRAM, memory accesses will block and there is no point trying to parallelize the sum.